Electro-Optical Router Chiplet Breakthrough at ISSCC

At ISSCC this week, researchers from CEA-List and CEA-Leti introduced a major step forward in chiplet-based optical networking: an electro-optical router chiplet capable of dynamic, frame-level routing integrated directly with CMOS control logic.

The paper, titled:

“A 3.19pJ/bit Electro-Optical Router with 18ns Setup Frame-Level Routing and 1–6 Wavelength Flexible Link Capacity for Photonic Interposers”

demonstrates a router fabricated in 28nm CMOS technology, implemented on a photonic interposer, and capable of establishing optical communication paths in just 18 nanoseconds.

This development brings nanosecond-scale dynamic optical routing inside chip packages — something previously achievable only with short electrical links.

Why This Electro-Optical Router Chiplet Matters

Modern chiplet architectures increasingly rely on advanced packaging techniques such as 2.5D interposers to interconnect compute, memory, and accelerator dies. As system complexity increases — especially in HPC and AI — traditional electrical interconnects face challenges in:

• Energy efficiency

• Latency

• Bandwidth scaling

• Signal integrity over distance

The electro-optical router chiplet addresses these constraints by enabling optical communication across centimeter-scale interposers while maintaining ultra-low latency and high energy efficiency.

Instead of routing all data electrically across short distances, optical paths can now be dynamically established across the interposer fabric.

Technical Highlights of the ISSCC Demonstration

The router integrates multiple core functions directly with silicon photonics:

• Optical switching

• Routing control logic

• SerDes (Serializer/Deserializer)

• Clocking circuitry

All components are tightly integrated in a 28nm CMOS implementation.

Key Performance Metrics

These figures demonstrate a dense, power-efficient architecture that can scale across large chiplet fabrics.

Frame-Level Dynamic Optical Routing

One of the most notable aspects of this electro-optical router chiplet is its frame-level routing capability.

Unlike static optical links, this system allows:

• Optical paths to be established on demand

• Links to be torn down dynamically

• Capacity scaling per application requirements

Each link can select between one and six wavelengths, allowing flexible bandwidth allocation depending on workload.

This means the optical bandwidth is not fixed. Instead, it adapts dynamically to application needs — improving resource utilization while maintaining ultra-low latency.

Energy Efficiency and Integration Density

With an energy efficiency of 3.19 picojoules per bit, the router achieves performance levels suitable for next-generation AI and HPC systems where interconnect power can dominate total energy budgets.

The active area per link is only 0.007 mm², enabling dense integration of optical endpoints close to:

• Compute cores

• Memory dies

• Accelerator tiles

The architecture uses:

• Analogue optical drivers

• Standard-cell-based SerDes

• Integrated clocking circuits

This combination allows tight placement of photonic interfaces next to logic resources without requiring exotic design flows.

From Electrical Constraints to Optical Freedom

In conventional multi-die systems, electrical interconnect length directly impacts:

• Latency

• Power consumption

• Signal degradation

As a result, system architects often force memory resources to reside physically close to compute cores to minimize routing cost.

The introduction of a dynamically routed electro-optical router chiplet changes this constraint.

Instead of optimizing for electrical reach, architects can now treat memory and compute resources across the interposer as part of a unified, high-reach optical fabric — without sacrificing latency or energy efficiency.

This represents a shift from proximity-based design to fabric-based architecture.

Implications for HPC and AI Accelerators

High-performance computing and AI accelerators increasingly demand:

• Massive memory bandwidth

• Scalable interconnect fabrics

• Flexible topology management

• Energy-efficient data movement

Dynamic optical routing inside the package enables:

• Adaptive bandwidth allocation

• Rapid topology reconfiguration

• Lower power per transferred bit

• Reduced congestion in dense multi-chip systems

This could prove particularly valuable for:

• AI training clusters

• Large language model accelerators

• Data-centric HPC workloads

• Chiplet-based heterogeneous systems

By enabling nanosecond-scale optical path setup, the electro-optical router chiplet brings optical networking performance closer to electrical responsiveness.

The Future of Photonic Interposers

The demonstration at ISSCC shows that optical interconnects are no longer limited to board-level or rack-level networking.

Instead, photonics is moving inside the package.

With dynamic wavelength selection and frame-level control, optical interposers could become:

• Reconfigurable fabrics

• Adaptive bandwidth networks

• Energy-scalable interconnect layers

This marks a step toward chip packages that behave more like miniature optical data centers — dynamically allocating bandwidth where needed.

The electro-optical router chiplet presented by CEA-List and CEA-Leti at ISSCC represents a significant advancement in chiplet-based optical networking.

By combining:

• 18ns optical path setup

• 3.19 pJ/bit energy efficiency

• Flexible 1–6 wavelength selection

• Ultra-compact integration

the technology enables nanosecond-scale dynamic optical routing across photonic interposers.

As chiplet architectures continue to scale in complexity — particularly in AI and HPC systems — solutions like this electro-optical router chiplet could redefine how compute and memory resources are interconnected inside advanced semiconductor packages.